##### Improving Analog Simulation Speed Using Verilog-A / Verilog-AMS Without Compromising Circuit Accuracy

- Mixed Signal Design
- Aug 22, 2017 8:33:00 AM

Analog circuit simulation is an essential requirement for mixed signal IC verification, but simulating circuits of any significant size at the transistor level with a low level simulator like SPICE can take prohibitively long periods of time. Furthermore, simulating mixed analog and digital systems at different abstraction levels is not possible with an analog only simulator like SPICE.

Verilog-AMS, an extension of Verilog, was introduced to address these problems. It includes the capability to model analog and mixed-signal systems with higher level behavioral descriptions. It is tightly coupled with the Verilog event loop, enabling mixed digital and analog simulations.

Verilog-A is the analog subset of Verilog-AMS. The behavioral analog descriptions of Verilog-A will almost always simulate faster than SPICE level models; but often at the expense of accuracy. What do you do if you can't sacrifice the accuracy?

A solution we frequently use at Intrinsix employs a table lookup mechanism using the Verilog-A *$table_model* function*.* Since table lookups are efficient, modeling the behavior of an analog circuit as a lookup can give high performance while retaining high accuracy, as long as the values in the table are accurate.

*The $table_model function*

The $table_model function maps a set of independent variables onto a dependent result. The inputs to $table_model are a set of sample points, and a *control string* which specifies how interpolation and extrapolation is performed. The interpolation algorithm specifies how results are determined for points between those supplied in the table. The extrapolation algorithm specifies how results are determined for points beyond the range of the supplied data.

**The table of points can be derived in a number of ways:**

- from an equation, or set of equations,
- from a simulation (SPICE, Matlab, etc),
- from measurements taken in the lab, or
- from a data sheet.

Obviously, the accuracy of the result will depend on the accuracy of the sample points. Results taken from lab measurements can be very accurate, whereas results taken from a behavioral simulation may be less accurate.

Note that $table_model functions are similar in some respects to current and voltage piecewise linear sources (ipwl, vpwl) in SPICE. A key difference, though, is that table models allow results to be further processed before driving output pins. In addition, table models support an arbitrary number of independent variables, whereas ipwl and vpwl sources support only a single independent variable (time).

## When To Use Table Models

It doesn't always make sense to use a table model. If the analog behavior is easy to model in Verilog-A, and the accuracy is acceptable, then there's no need to complicate the process by using table models. But if accuracy is required, and the analog behavior is difficult or impossible to model to specification, then table models should be considered.

*Table Model Sample Points For A Photodiode*

We recently encountered an example of this when modeling a photodiode. The challenge was to model current through the photodiode circuit as a function of bias voltage and illumination (lux). Creating a Verilog-A model would have been fairly complicated and time consuming; but creating a table model was not difficult, because the measured, hardware-affirmed data was readily available. It was a straight forward process to parse and format the measured data into a table file, which could then be consumed directly by the $table_model function. The resulting model was relatively simple to create, accurate, and was perfect for testing the supporting electronics around the photodiode. Using this strategy, we were able to gain high confidence that the photodiode and supporting electronics would function as required in the ASIC.

## Considerations

There are a few things to consider when developing table models.

First, care must be taken when parsing and formatting the table data. The $table_model function requires a very specific format; incorrectly formatted tables can cause $table_model errors. Worse yet, misaligned or improperly formatted data could be interpreted incorrectly, causing subtle errors in the simulation results.

Second, the user should be aware that too few sample points can cause interpolation errors. The number of sample points must be sufficient to reduce the error to an acceptable level. The Verilog-AMS 2.4 Reference Manual (section 9.2.1) gives a good explanation of how interpolation works. It can be used to help determine the required number of points.

Despite these complexities, table models are a useful tool for creating highly accurate models, without sacrificing performance. If you have used table models for a recent simulation project, please comment on this article and share your experiences.

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